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esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 1/54 sgram 256k x 32 bit x 2 banks synchronous graphic ram features y jedec standard 3.3v power supply y lvttl compatible with multiplexed address y dual bank / pulse ras y mrs cycle with address key programs - cas latency ( 2, 3 ) - burst length ( 1, 2, 4, 8 & full page ) - burst type ( sequential & interleave ) y all inputs are sampled at the positive going edge of the system clock y burst read single-bit write operation y dqm 0-3 for byte masking y auto & self refresh y 32ms refresh period (2k cycle) y 100 pin qfp graphic features y smrs cycle - load mask register - load color register y write per bit y block write (8 columns) general description the M32L1632512A is 16, 777, 216 bits synchro - nous high data rate dynamic ram organized as 2 x 262, 144 words by 32 bits, fabricated with esmt?s high performance cmos technology. synchronous design allows precise cycl e control with the use of system clock. i/o transactions are possible on every clock cycle. range of operating frequencies , progra - mmable burst length, and programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications. write per bit and 8 columns block write improves performance in graphic systems. ordering information part no. cycle time clock frequency access time@cl=3 t rdl (clk) M32L1632512A-5q 5ns 200mhz 4.5ns 1 M32L1632512A-5sq 5ns 200mhz 4.5ns 2 M32L1632512A-6q 6ns 166mhz 5.5ns 1 M32L1632512A-6sq 6ns 166mhz 5.5ns 2 M32L1632512A-7q 7ns 143mhz 6.0ns 1 M32L1632512A-7sq 7ns 143mhz 6.0ns 2 M32L1632512A-8q 8ns 125mhz 6.5ns 1 M32L1632512A-8sq 8ns 125mhz 6.5ns 2
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 2/54 functional block diagram pin configuration (top view) block write control logic dqmi write control logic mask mux mask register color register column mask input buffer programing register column decorder sense amplifier 256kx32 cell array 256kx32 cell array output buffer row decorder bank selection serial counter column address buffer row address buffer refresh counter address register clock address(a 0 ~a 10 ) dqmi dqi (i=0~31) timing register clk cke cs ras cas we dsf dqmi latency & burst length dq28 vddq dq27 dq26 v ssq dq25 dq24 dq15 dq14 v ddq dq13 dq12 v ssq dq11 v ss dq10 v dd dq9 dq8 v ssq dq m3 v ddq n. c cl k cke dq m1 n. c a 9 dsf 80 79 78 77 75 74 76 72 71 73 69 70 68 65 67 64 66 62 61 63 59 58 60 56 55 57 53 54 52 v ddq 51 dq3 dq4 dq5 dq 6 dq 7 v ssq dq16 dq17 v ddq dq18 v ssq dq19 dq20 v ss dq21 v dd dq22 dq23 v ssq dq m0 dq m2 v ddq v ddq we ba(a 10 ) a 8 1 2 3 4 6 7 5 9 10 8 12 11 13 14 16 17 15 19 20 18 22 23 21 25 26 24 28 27 29 30 v ddq cas ras cs 50 49 48 47 45 44 46 42 41 43 39 40 38 37 35 34 36 32 31 33 81 82 83 84 86 87 85 89 90 88 92 91 93 94 96 97 95 99 100 98 dq29 dq 0 v dd dq 1 v ssq dq 2 v ssq dq30 dq31 v ss n. c n. c n. c n. c n. c n. c
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esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 3/54 pin description pin name input function clk system clock active on the positive going edge to sample all inputs cs chip select disables or enable device operation by masking or enabling all inputs except clk, cke and dqmi cke clock enable masks system clock to freeze oper ation from the ne xt clock cycle. cke should be enabled at least one clock+ t ss prior to new command. disable input buffers for power down in standby. a0 ~ a9 address row / column addresses are multiplexed on the same pins. row address : ra0~ra9, column address : ca0~ca7 a10(ba) bank select address selects bank to be activated during row address latch time. selects bank for read / write during column address latch time. ras row address strobe latches row addresses on the positive going edge of the clk with ras low. enables row access & precharge. cas column address strobe latches column address on the positive going edge of the clk with cas low. enables column access. we write enable enables write operation and row precharge. dqmi data input/output mask makes data output hi-z, t shz after the clock and masks the output. blocks data input when dqm active. (byte masking) dqi data input/output data inputs/outputs are multiplexed on the same pins. dsf define special/ function enables write per bit, block write and special mode register set. v dd /v ss power supply/ ground v ddq /v ssq data output power/ground absolute maximum ratings (voltage referenced to v ss ) parameter symbol value unit voltage on any pin relative to v ss v in , v out -1.0 ~ 4.6 v voltage on v dd supply relative to v ss v dd , v ddq -1.0 ~ 4.6 v storage temperature t stg -55 ~ +150 i power dissipation p d 1w short circuit current i os 50 ma note : permanent device damage may occur if ?a bsolute maximum ratings? are exceeded. functional operation should be restri cted to recommended operating condition. exposure to higher than recommended voltage fo r extended periods of time could affect device reliability.
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 4/54 dc operating conditions recommended operating conditions (voltage referenced to v ss = 0v) parameter symbol min typ max unit note supply voltage v dd , v ddq 3.0 3.3 3.6 v input high voltage v ih 2.0 3.0 v dd +0.3 v input low voltage v il -0.3 0 0.8 v note 1 output high voltage v oh 2.4 - - v i oh = -2ma output low voltage v ol -- 0.4vi ol = 2ma input leakage current i il -5 - 5 a note 2 output leakage current i ol -5 - 5 a note 3 output loading condition see fig 1 note: 1. v il (min) = -1.5v ac (pulse width 5ns) 2. any input 0v v in v dd + 0.3v, all other pins are not under test = 0v. 4. dout is disabled, 0v v out v dd . capacitance (v dd /v ddq = 3.3v, t a = 25 c , f = 1mh z ) parameter symbol min max unit input capacitance (a0 ~ a10) c in1 -4pf input capacitance (clk, cke, cs , ras , cas , we , dsf& dqm0-3) c in2 -4pf data input/output capacitance (dq0 ~ dq31) c out -5pf decoupling capacitance guide line recommended decoupling capacitance added to power line at board. parameter symbol value unit decoupling capacitance between v dd & v ss c dc1 0.1+0.01 uf decoupling capacitance between v ddq & v ssq c dc2 0.1+0.01 uf *note: 1. v dd and v ddq pins are separated each other. all v dd pins are connected in chip. all v ddq pins are connected in chip. 2. v ss and v ssq pins are separated each other. all v ss pins are connected in chip. all v ssq pins are connected in chip.
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 5/54 dc characteristics recommended operating condition unless otherwise noted, t a = 0 to 70 c v ih(min) /v il(max) =2.0v/0.8v version unit note parameter symbol test condition cas latency -5/5s -6/6s -7/7s -8/8s 3 230 210 195 170 operating current (one bank active) i cc1 burst length = 1 t rc t rc(min) , t cc t cc(min) i ol = 0 ma 2 230 210 195 170 ma 1 i cc2 p cke v il(max) , t cc = 15ns 222 2 precharge standby current in power-down mode i cc2 ps cke v il(max) , clk v il(max) , t cc = 222 2 ma i cc2 n cke v ih(min) , cs v ih(min) , t cc = 15ns input signals are ch anged one time during 30ns 35 35 35 35 precharge standby current in non power-down mode i cc2 ns cke v ih(min) , clk v il(max) , t cc = input signals are stable 15 15 15 15 ma i cc3 p cke v il(max) , t cc = 15ns 333 3 active standby current in power-down mode i cc3 ps cke v il(min) , clk v il(max) , t cc = 333 3 ma i cc3 n cke v ih(min) , cs v ih(min) , t cc = 15ns input signals are ch anged one time during 30ns 60 60 60 60 ma active standby current in non power-down mode (one bank active) i cc3 ns cke v ih(min) , clk v il(max) , t cc = input signals are stable 20 20 20 20 3 230 210 195 170 operating current (burst mode) i cc4 i ol = 0 ma, page burst all banks activated, t ccd = t ccd (min) 2 230 210 195 170 ma 1, 2 3 190 170 160 150 refresh current i cc5 t rc t rc(min) 2 190 170 160 150 ma 3 self refresh current i cc6 cke 0.2v 2 2 2 2 ma operating current (one bank block write) i cc7 t cc t cc(min), i ol = 0 ma, t bwc(min) 220 200 190 180 ma 4 *note : 1. measured with outputs open. 2. assumes minimum column address update cycle t ccd(min). 3. refresh period is 32ms. 4. assumes minimum column address update cycle t bwc(min).
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 6/54 ac operating test conditions (v dd = 3.3v 0.3v, t a = 0 to 70 c ) parameter value ac input levels v ih /v il = 2.4v/0.4v input timing measurement reference level 1.4v input rise and fall-time (see note3) t r / t f = 1ns/1ns output timing measurement reference level 1.4v output load condition see fig. 2 (fig. 1) dc output load circuit (fig. 2) ac output load circuit ac characteristics (ac operating conditions unless otherwise noted) -5/5s -6/6s -7/7s -8/8s unit note parameter symbol min max min max min max min max cas latency =3 5678 clk cycle time cas latency =2 t cc 7.5 1000 8 1000 10 1000 12 1000 ns 1 cas latency =3 -4.5-5.5- 6 -6.5 clk to valid output delay cas latency =2 t sac -5-6-7-8 ns 1, 2 cas latency =3 2222 ns output data hold time cas latency =2 t oh 2222 ns 2 clk high pulse width t ch 2 2 2.5 3 ns 3 clk low pulse width t cl 2 2 2.5 3 ns 3 input setup time t ss 2222.5 ns3 input hold time t sh 1111 ns3 clk to output in low-z t slz 1111 ns2 cas latency =3 - 5 - 5.5 - 6 - 6.5 clk to output in hi-z cas latency =2 t shz -5-6-7-8 ns * all ac parameters are measured from half to half. output 870 v oh (dc) =2.4v , i oh = -2 ma v ol (dc) =0.4v , i ol = 2 ma output 30pf z0 =50 30pf 50 v ref = 1.4v 3.3v 1200
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 7/54 *note : 1. parameters depend on programmed cas latency. 2. if clock rising time is longer than 1ns, (tr/ 2 - 0.5) ns should be added to the parameter. 3. assumed input rising and falling time (tr & tf) = 1ns. if tr & tf is longer 1ns, transient time compensation should be considered. i.e., [(tr + tf)/2 - 1] ns shou ld be added to the parameter. operating ac parameter (ac operating conditions unless otherwise noted) version unit note parameter symbol -5 -5s -6 -6s -7 -7s -8 -8s row active to row active delay t rrd(min) 10 12 14 16 1 ras to cas delay t rcd(min) 15 18 20 20 ns 1 row precharge time t rp(min) 15 18 21 24 ns 1 t ras(min) 40 40 42 48 ns 1 row active time t ras(max) 100 us row cycle time t rc(min) 55 60 63 72 ns 1 last data in to new col. address delay t cdl(min) 1 clk 2 last data in to row precharge t rdl(min) 1212 1212 clk 2 block write data-in to pre command delay t bpl(min) 10 12 14 16 ns block write data-in to active (ref) command period (auto precharge) t bal(min) 25 30 35 40 ns last data to burst stop t bdl(min) 1 clk 2 col. address to col. address delay t ccd(min) 1clk3 block write cycle time t bwc(min) 2222clk4 cas latency = 3 2 clk 5 number of valid output data cas latency = 2 1 note : 1. the minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. minimum delay is required to complete write. 3. all parts allow every cycle column address change except block write cycle. 4. this parameter means minimum cas to cas delay at block write cycle only. 5. in case of row precharge interrupt, auto precharge and read burst stop.
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 8/54 frequency vs. ac paramet er relationship table M32L1632512A-5q ( * : -5sq ) (unit : number of clock) t rc t ras t rp t rrd t rcd t ccd t cdl t rdl * t rdl frequency cas latency 55ns 40ns 15ns 10ns 15ns 5ns 5ns 5ns 10ns 200 mhz(5.0ns) 3 11 8 3 2 3 1 1 1 2 166 mhz(6.0ns) 3 10 7 3 2 3 1 1 1 2 143 mhz(7.0ns )3 863231112 125 mhz(8.0ns )2 752221112 M32L1632512A-6q ( * : -6sq ) (unit : number of clock) t rc t ras t rp t rrd t rcd t ccd t cdl t rdl * t rdl frequency cas latency 60ns 40ns 18ns 12ns 18ns 6ns 6ns 6ns 12ns 166 mhz(6.0ns) 3 10 7 3 2 3 1 1 1 2 143 mhz(7.0ns )3 963231112 125 mhz(8.0ns )2 853231112 100 mhz(10.0ns )2 642221112 M32L1632512A-7q ( * : -7sq ) (unit : number of clock) t rc t ras t rp t rrd t rcd t ccd t cdl t rdl * t rdl frequency cas latency 63ns 42ns 21ns 14ns 20ns 7ns 7ns 7ns 14ns 143 mhz(7.0ns ) 3 963231112 125 mhz(8.0ns ) 3 863231112 100 mhz(10.0ns )2 753221112 83 mhz(12.0ns ) 2 642221112 M32L1632512A-8q ( * : -8sq ) (unit : number of clock) t rc t ras t rp t rrd t rcd t ccd t cdl t rdl * t rdl frequency cas latency 72ns 48ns 24ns 16ns 20ns 8ns 8ns 8ns 16ns 125 mhz(8.0ns ) 3 963231112 100 mhz(10.0ns )3 853221112 83 mhz(12.0ns ) 2 642221112 75 mhz(13.4ns ) 2 642221112
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 9/54 simplified truth table command cken-1 cken cs ras cas we dsf dqm a10 a9 a8~a0 note mode register set l1, 2 register special mode register se t h xllll h xop code 1, 2, 7 auto refresh h 3 entry h l lllhlx x 3 lhhh 3 refresh self refresh exit lh hxxx xx x 3 write per bit disable l 4, 5 bank active & row addr. write per bit enable hxllhh h x v row address 4,5,9 auto precharge disable l4 read & column address auto precharge enable h xlhlhlxv h column address 4, 6 auto precharge disable l4, 5 write & column address auto precharge enable h xlhlllxv h column address 4,5,6,9 auto precharge disable l4, 5 block write & column address auto precharge enable h xlhl lhxv h column address 4,5,6,9 burst stop h x l h h l l x x 7 bank selection vl precharge both banks hxllhllx xh x lhhh entry h l hxxx xx clock suspend or active power down exit l h xxxx xx x lhhh entry h l hxxx xx lvvvv precharge power down mode exit l h hxxxx x x dqm h x v x 8 lhhh xx no operation command h x hxxx x (v = valid, x = don?t care. h = logic high, l = logic low ) note : 1.op code : operand code a0~a10 : program keys. (@ mrs) a5, a6 : lmr & lcr select. (@ smrs) color register exists only one per dqi which both banks share. so does mask register. color or mask is loaded into chip through dq pin. 2.mrs can be issued only at both banks precharge state. smrs can be issued only if dq?s are idle. a new command can be issued at the next clock of mrs/smrs.
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 10/54 3.auto refresh functions as sa me as cbr refresh of dram. the automatical precharge without row pr echarge of command is meant by ?auto?. auto/self refresh can be issued on ly at both banks precharge state. 4.a10 : bank select address. if ?low? at read, (block) write, row active and precharge, bank a is selected. if ?high? at read, (block) write, row act ive and precharge, bank b is selected. if a9 is ?high? at row precharge, a10 is ignored and both banks are selected. 5.it is determined at row active cycle. whether normal/block write operates in write per bit mode or not. for a bank write, at a bank row active, for b bank write, at b bank row active. terminology : write per bit = i/o mask (block) write with write per bit mode = masked (block) write 6.during burst read or write with auto precharge, new read/(block) write command cannot be issued. another bank read/(block) write command can be issued at t rp after the end of burst. 7.burst stop command is valid for all burst length. 8.dqm sampled at positive going edge of a clk. masks the data-in at the very clk (write dqm latency is 0) but makes hi-z state the data-out of 2 clk cycles after.(read dqm latency is 2) 9.graphic features added to sdram?s original features. if dsf is tied to low, graphic functions are di sabled and chip operates as a 16m sdram with 32 dq?s. sgram vs sdram sdram function mrs bank active write dsf l h l h l h sgram function mrs smrs bank active with write per bit disable bank active with write per bit enable normal write block write if dsf is low. sgram functionality is identical to sdram functionality. sgram can be uesed as an unified me mory by the appropriate dsf control ? sgram = graphic memory + main memory. mode register field ta ble to program modes register programmed with mrs address a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 function rfu w.b.l tm cas latency bt burst length (note1) (note2)
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 11/54 test mode cas latency burst type burst length a8 a7 type a6 a5 a4 latency a3 type a2 a1 a0 bt = 0 bt = 1 0 0 mode register set 0 0 0 reserved 0 sequential 0 0 0 1 reserved 0 1 vendor 0 0 1 - 1 interleave 0 0 1 2 reserved 10 use 010 2 010 4 4 11 only 011 3 011 8 8 write burst length 1 0 0 reserved 1 0 0 reserved reserved a9 length 1 0 1 reserved 1 0 1 reserved reserved 0 burst 1 1 0 reserved 1 1 0 reserved reserved 1 single bit 1 1 1 reserved 1 1 1 256(full) reserved (note 3) special mode register programmed with smrs address a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 function x lc lm x load color load mask a6 function a5 function 0 disable 0 disable 1 enable 1 enable (note 4) power up sequence 1.apply power and start clock, attempt to maintain cke = ?h?, dqm = ?h? and the other pin are nop condition at the inputs. 2. maintain stable power, stable clock a nd nop input condition for a minimum of 200 s. 3. issue precharge commands for all banks of the devices. 4. issue 2 or more auto-refresh commands. 5. issue a mode register set command to initialize the mode register. cf.) sequence of 4 & 5 may be changed. the device is now ready for normal operation. note : 1. rfu(reserved for future use) should stay ?0? during mrs cycle. 2. if a9 is high during mrs cycle, ?burst r ead single bit write? function will be enabled. 3. the full column burst (256bit) is availabl e only at sequential mode of burst type. 4. if lc and lm both high (1), data of mask and color register will be unknown.
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 12/54 burst sequence (burst length = 4) initial address a1 a0 sequential interleave 0001230123 0112301032 1023012301 1130123210 burst sequence (burst length = 8) initial address a2 a1 a0 sequential interleave 0 0 0 0123456701234567 0 0 1 1234567010325476 0 1 0 2345670123016745 0 1 1 3456701232107654 1 0 0 4567012345670123 1 0 1 5670123454761032 1 1 0 6701234567452301 1 1 1 7012345676543210 pixel to dq mapping (at block write) column address 3 byte 2 byte 1 byte 0 byte a2 a1 a0 i/o31~ i/o24 i/o23~ i/o16 i/o15~ i/o8 i/o7~ i/o0 0 0 0 dq24 dq16 dq8 dq0 0 0 1 dq25 dq17 dq9 dq1 0 1 0 dq26 dq18 dq10 dq2 0 1 1 dq27 dq19 dq11 dq3 1 0 0 dq28 dq20 dq12 dq4 1 0 1 dq29 dq21 dq13 dq5 1 1 0 dq30 dq22 dq14 dq6 1 1 1 dq31 dq23 dq15 dq7
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 13/54 device operations clock (clk) the clock input is used as the reference for all sgram operations. all operations are synchronized to the posi tive going edge of the clock. the clock transitions must be monotonic between v il and v ih . during operation with cke high all inputs are assumed to be in valid state (low or high) for the durati on of setup and hold time around positive edge of the clock for proper functionality and i cc specifications. clock enable(cke) the clock enable (cke) gates the clock onto sgram. if cke goes low synchronously with clock (set-up and hold time same as other inputs), the internal clock suspended from the next clock cycle and the state of out put and burst address is frozen as long as the cke remains low. all other inputs are ignored from th e next clock cycle after cke goes low. when both banks are in the idle state and cke goes low synchronously with clock, the sgram enters the pow er down mode from the next clock cycle. the sgram remains in the power down mode ignoring the other inputs as long as cke remains low. the power down exit is synchronous as the internal clock is suspended. when cke goes high at least ? t ss +1clock? before the high going edge of the clock, then the sgram becomes active from the same clock edge accepting all the input commands. bank select (a10) this sgram is organized as two independent banks of 262, 144 words x 32 bits memory arrays. the a10 inputs are latched at the time of assertion of ras and cas to select the bank to be used for the operation. when a10 is asserted low, bank a is selected. when a10 is latched high, bank b is selected. the banks select a10 is latched at bank activate, read, write, mode register set and precharge operations. address inputs (a0~a9) the 18 address bits are required to decode the 262,144 word locations are multiplexed into 10 address input pins (a0~a9). the 10 bit row address is latched along with ras and a10 during bank activate command. the 8 bit column address is latched along with cas, we and a10 during read or write command. nop and device deselect when ras , cas and we are high, the sgram performs no operation (nop). nop does not initiate any new operation, but is needed to complete operations which require more than single clock cycle like bank activate, burst read, auto refresh, etc. the device deselect is also a nop and is entered by asserting cs high. cs high disables the command decoder so that ras , cas, we , dsf and all the address inputs are ignored. power-up the following sequence is recommended for power up 1.power must be applied to either cke and dqm inputs to pull them high and other pins are nop condition at the inputs before or along with v dd (and v ddq ) supply. the clock signal must also be asserted at the same time. 2.after v dd reaches the desired voltage, a minimum pause of 200 microseconds is required with inputs in nop condition. 3.both banks must be precharged now. 4.perform a minimum of 2 auto refresh cycles to stabilize the internal circuitry. 5.perform a mode register set cycle to program the cas latency, burst length and
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 14/54 device operations (continued) burst type as the default value of mode register is undefined. at the end of one cloc k cycle from the mode register set cycle, the de vice is ready for operation. when the above sequence is used for power-up, all the outputs will be in hi gh impedance state. the high impedance of outputs is not guaranteed in any other power-up sequence. cf.) sequence of 4 & 5 may be changed. mode register set (mrs) the mode register stores th e data for controlling the various operating modes of sgram. it programs the cas latency, burst type, addressing, burst length, test mode and various vendor specific options to make sgram useful for variety of different applications. th e default value of the mode register is not de fined, therefore the mode register must be writte n after power up to operate the sgram. the mode register is written by asserting low on cs , ras , cas, we and dsf (the sgram should be in active mode with cke already high prior to writing the mode register). the state of a ddress pins a0~a9 and a10 in the same cycle as cs , ras , cas, we and dsf going low is the data written in the mode register. one clock cycles is required to complete the write in the mode register. the mode register contents can be changed using the same command and clock cycle require ments during operation as long as both banks are in the idle state. the mode register is divided into various fields depending on functionality. the bur st length field uses a0~a2, burst type uses a3, cas latency (read latency from column address) a4~a6, a7~a8 and a10 are uses for vendor specific options or test mode use. and the write burst length is programmed using a9. a7~a8 and a10 must be set to low for normal sgram operation. refer to the table for specific code s for various burst length, addressing modes and cas latencies. bank activate the bank activate command is used to select a random row in an idle bank. by asserting low on ras and cs with desired row and bank addresses, a row access is initiated. the read or write operation can occur after a time delay of t rcd (min) from the time of bank activation. t rcd (min) is the internal timing parameter of sgram, therefore it is dependent on operating clock frequency. the minimum number of clock cycles required between bank activate and read or write command should be calculated by dividing t rcd (min) with cycle time of the clock and then rounding of the result to the next higher integer. the sg ram has two internal banks in the same chip and shares part of the internal circuitry to reduce chip area, therefore it restricts the activ ation of both banks immediately. also the noise generated during sensing of each bank of sgram is high requiring some time for power supplies to recover before another bank can be sensed reliably. t rrd (min) specifies the minimum time required between activating different bank. the number of clock cycles required between different bank activation must be calculated similar to t rcd specification. the minimum time required for the bank to be active to initiate sensing and restoring the complete row of dynamic cells is determined by t ras (min) . every sgram bank activate command must satisfy t ras (min) specification before a precharge command to that active bank can be asserted. the maximum time any bank can be in the active state is determined by t ras (max). the number of cycles for both t ras(min) and t ras (max) can be calculated similar to t rcd specification. burst read the burst read command is used to access burst of data on consecutive clock cycles from an
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 15/54 device operations (continued) active row in an activ e bank. the burst read command is issued by asserting low on cs and cas with we being high on the positive edge of the clock. the bank must be active for at least t rcd (min) before the burst read command is issued. the first output appears in cas latency number of clock cycles after the issu e of burst read command. the burst length, burst se quence and latency from the burst read command is determined by the mode register which is alre ady programmed. the burst read can be initiated on a ny column address of the active row. the address wr aps around if the initial address does not start from a boundary such that number of outputs from each i/o are equal to the burst length programmed in the mode register. the output goes into high-imped ance at the end of burst, unless a new burst read was initiated to keep the data output gapless. the burst read can be terminated by issuing anot her burst read or burst write in the same bank or the other active bank or a precharge command to the same bank. the burst stop command is valid for all burst length. burst write the burst write command is similar to burst read command, and is used to write data into the sgram on consecutive clock cycles in adjacent addresses depending on bu rst length and burst sequence. by asserting low on cs , cas and we with valid column address, a write burst is initiated. the data inputs ar e provided for the initial address in the same cloc k cycle as the burst write command. the input buffer is deselected at the end of the burst length, even though the internal writing may not have been completed yet. the writing can not complete to burst leng th. the burst write can be terminated by issuing a burst read and dqm for blocking data inputs or bu rst write in the same or the other active bank. the write burst can also be terminated by using dqm for blocking data and precharging the bank ? t rdl ? after the last data input to be written into the active row. see dqm operation also. dqm operation the dqm is used mask input and output operations. it works similar to oe during operation and inhibits writing during write operation. the read latency is two cycles from dqm and zero cycle for write, which means dqm masking occurs two cycles later in read cycle and occurs in the same cycle during write cycle. dqm operation is synchronous with the clock. the dqm signal is important during burst interrupts of write with read or precharge in the sgram. due to asynchronous nature of the internal write, the dqm operation is critical to avoid unwanted or incomplete writes when the complete burst write is required. dqm is also used for device sel ection and bus control in a memory system. dqm0 controls dq0 to dq7, dqm1 controls dq8 to dq15, dqm2 controls dq16 to dq23, dqm3 controls dq24 to dq31. dqm masks the dq?s by a byte regardless that the corr esponding dq?s are in a state of wpb masking or pixel masking. please refer to dqm timing diagram also. precharge the precharge is perf ormed on an active bank by asserting low on cs , ras , we and a9 with valid a10 of the bank to be precharged. the precharge command can be asserted anytime after t ras (min) is satisfy from the bank activate command in the desired bank. ? t rp ? is defined as the minimum time required to precharge a bank.
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 16/54 device operations (continued) the minimum number of cl ock cycles required to complete row precharge is calculated by dividing ? t rp ? with clock cycle time and rounding up to the next higher integer. care should be taken to make sure that burst write is completed or dqm is used to inhibit writing befo re precharge command is asserted. the maximum time any bank can be active is specified by t ras (max). therefore, each bank has to be precharged within t ras (max) from the bank activate command. at the end of precharge, the bank enters the idle state and is ready to be activated again. entry to power down, auto refresh, self refresh and mode register set et c. is possible only when both banks are in idle state. auto precharge the precharge operation ca n also be performed by using auto precharge. the sgram internally generates the timing to satisfy t ras (min) and ? t rp ? for the programmed burst length and cas latency. the auto precharge command is issued at the same time as burst read or burst write by asserting high on a9. if burst read or burst write command is issued with low on a9, the bank is left active until a new command is asserted. once auto precharge command is given, no new command are possible to that particular bank until the bank achieves idle state. both banks precharge both banks can be prechar ged at the same time by using precharge all command. asserting low on cs , ras and we with high on a9 after all banks have satisfied t ras (min) requirement, performs precharge on both banks. at the end of t rp after performing precharge all, all banks are in idle state. auto refresh the storage cells of sgram need to be refreshed every 32ms to maintain data. an auto refresh cycle accomplishes refresh of a single row of storage cells. the internal counter increments automatically on every auto refresh cycle to refresh all the rows. an auto refresh command is issued by asserting low on cs , ras and cas with high on cke and we . the auto refresh command can only be asserted with both banks being in idle state and the device is not in power down mode (cke is high in the previous cycle). the time required to complete the auto refresh operation is specified by t rc (min) . the minimum number of clock cycles required can be calculated by driving t rc with clock cycle time and them rounding up to the next higher integer. the auto refresh command must be followed by nop?s until the auto refresh operation is completed. both banks will be in the idle state at the end of auto refresh operation. the auto refresh is the preferred refresh mode when the sgram is being used for normal data transactions. the auto refresh cycle can be performed once in 15.6us or the burst of 2048 auto refresh cycles in 32ms. self refresh the self refresh is another refresh mode available in the sgram. the self refresh is the preferred refresh mode for data retention and low power operation of sgram. in self refresh mode, the sgram disables the internal clock and all the input buffers except cke. the refresh addressing and timing is internally generated to reduce power consumption. the self refresh mode is entered from all banks idle state by asserting low on cs , ras , cas and cke with high on we . once the self refresh mode is entered, only cke state
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 17/54 device operations (continued) being low matters, all the other inputs including clock are ignored to remain in the refresh. the self refresh is exited by restarting the external clock and then asserting high on cke. this must be followed by nop?s for a minimum time of t rc before the sgram reaches idle state to begin normal operation. if the system uses burst auto refresh during normal opera tion, it is recommended to use burst 2048 auto refr esh cycles immediately after exiting self refresh. define special function(dsf) the dsf controls the graphic applications of sgram. if dsf is tied to low, sgram functions as 256k x 32 x 2 bank sdram. sgram can be used as an unified memo ry by the appropriate dsf command. all the graphic function mode can be entered only by setting dsf high when issuing commands which otherwise would be normal sdram commands. sdram functions such as ras active, write and wcbr change to sgram functions such as ras active with wpb, block write and swcbr respectively, see the sessions below for the graphic functions that dsf controls. special mode register set(smrs) there are two kinds of sp ecial mode registers in sgram. one is color re gister and the other is mask register. those usage will be explained at ?write per bit? and ?block write? session. when a5 and dsf goes high in the same cycle as cs , ras , cas and we going low, load color register is filled with color data for associated dq?s through the dq pins. if both a5 and a6 are high at smrs, data of mask and color cycle is required to complete the write in the mask register and the color register at lmr and lcr respectively. the next color of lmr and lcr, a new commands can be issued. smrs, compared with mrs, can be issued at the active state under the condition that dq?s ar e idle. as in write operation, smrs accepts the data needed through dq pins. therefore it should be attended not to induce bus contention. the more detailed materials can be obtained by referring corresponding timing diagram. write per bit write per bit(i.e. i/o mask mode) for sgram is a function that selectively masks bits of data being written to the devices. the mask is stored in an internal register and applied to each bit of data written when enable. bank active command with dsf=high enable write per bit for the associated bank. the mask used for write per bit operations is stored in the mask register accessed by swcbr (special mode register set command). when a mask bit=0, the associated data bit is unaltered when a write command is executed and the write per bit has been enable for the bank being written. no additional timing conditions. write per bit writes can be either masking is the same for write per bit and non-wpb write. block write block write is a feature allowing the simultaneous writing of consecutive 8 columns of data within a ra m device during a single access cycle. during block write the data to be written comes from the internal ?color? register and dq i/o pins are used for independent column selection. the block of column to be written is aligned on 8 column boundaries and is defined by the column address with the 3 lsb?s ignored. write command with dsf=1 enable block write for the associated bank. the block width is 8 column where column =?n? bits for by ?n? part. the color register is the same width as the data port of the chip. it is width via a swcbr where data present on the dq pins is
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 18/54 device operations (continued) to be coupled into the in ternal color register. the color register provides the data masked by the dq column select, wpb mask (if enable), and dqm byte mask. column data ma sking (pixel masking) is provided on an individual column basis for each byte of data. the column mask is driven on the dq pins during a block write command. the dq column mask function is segmented on a per bit basis (i.e. dq [0:7] provided the column mask for data bits [0:7], dq [8:15] provided the column mask for data bits [8:15], dq0 masks column [0] for data bits[0:7], dq9 masks column [1] for data bits[8:15], etc). block writes are alwa ys non-burst independent of the burst length that ha s been programmed into to the mode register. if write per bit was enabled by the bank active command with dsf=1, then write per bit masking of the color register data is enabled. if write per bit was disabled by a bank active command with dsf=0, the wr ite per bit masking of the color register data is disabled. dqm masking provides independent da ta byte masking during normal write operations, except that the control is extended to the consecutive 8 columns of the block write. timing diagram to illustrate t bwc 1. 2clk cycle block write clock cke cs ras cas we dsf high 2 clk bw
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 19/54 summary of 2m byte sgram basic features and benefits features 256k x 32 x 2 sgram benefits interface synchronous better interaction between memory and system without wait-state of asynchronous dram. high speed vertical an d horizontal drawing. high operation frequency allows performance gain for scroll, fill, and bitblt. bank 2ea pseudo-infinite row length by on-chip interleaving operation. hidden row activation precharge. page depth /1 row 256 bit high speed vertical and horizontal drawing. total page depth 2048 bytes high speed vertical and horizontal drawing. burst length (read) 1, 2, 4, 8 full page programmable burst of 1, 2, 4, 8 and full page transfer per column address. 1, 2, 4, 8 full page programmable burst of 1, 2, 4, 8 and full page transfer per column address. burst length (write) brsw switch to burst length of 1 at write without mrs. burst type sequential & interleave compatible with intel and motorola cpu based system. cas latency 2, 3 programmable cas latency. block write 8 column high speed fill, clear, text with color registers. maximum 32 byte data transfer (e.g. for 8bpp : 32 pixels) with plane and byte masking functions. color register 1ea. a and b bank share. mask register 1 ea. write-per-bit capability (bit plane masking). a and b bank share. dqm0~3 byte masking (pixel masking for 8bpp system) for data-out/in write per bit each bit of the mask register directly controls a corresponding bit plane. mask function pixel mask at block write byte masking (pixel masking for 8bpp system) for color dqi. basic feature and fu nction description 1. clock suspend *note : cke to clk disable/enable=1 clock clk cmd cke internal clk dq(cl2) dq(cl3) rd q2 q0 q1 q3 q1 q0 q2 q3 d0 d1 d2 d3 d1 d2 d3 d0 wr masked by cke masked by cke 1) clock suspended during write (bl=4) 2) clock suspended during read (bl=4) not written suspended dout
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 20/54 2. dqm operation *note : 1. there are 4 dqmi (i = 0~3). each dqmi masks 8 dq?s. (1 byte, 1 pixel for 8bpp). 2. dqm masks data out hi-z after 2 clocks which should masked by cke ?l?. clk cmd dqm dq(cl2) dq(cl3) q0 q2 q3 q1 q2 q3 d0 d1 d3 d1 d3 d0 wr masked by dqm masked by dqm clk cmd dqm dq(cl2) dq(cl3) cke rd q0 q2 q4 hi-z hi-z hi-z q6 q7 q8 q5 q6 q7 q1 q3 hi-z hi-z hi-z hi-z hi-z 1)write mask (bl=4) 2)read mask (bl=4) dqm to data-in mask=0 clk dqm to data-out mask=2 3)dqm with clcok suspended (full page read) note2 rd
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 21/54 3. cas interrupt (i) *note : 1. by ?interrupt?, it is possible to stop burst read/write by external before the end of burst. by ? cas interrupt?, to stop burst read/write by cas access ; read, write and block write. 2. t ccd : cas to cas delay.(=1clk) 3. t cdl : last data in to new column address delay.(=1clk) 4.pixel : pixel mask. 5. t cc : clock cycle time. 6. t bwc : block write minimum cycle time. 7.other bank can be active or precharge. clk cmd add dq(cl2) dq(cl3) rd qb0 qb2 qa0 clk cmd add dq wr da0 db0 db1 rd a b qb1 qb3 qb0 qb2 qa0 qb3 qb1 t ccd *note 2 wr t ccd *note 2 a b t cdl *note 3 wr rd t ccd *note 2 a b da0 db0 db1 t cdl *note 3 da0 db0 db1 dq(cl3) dq(cl2) 1)read interrupted by read (bl=4) *note1 2)write interrupted by(block) write (bl=2) 3)write interrupted by read (bl=2) wr bw t ccd *note 2 a b dc0 pixel *note 4 t cdl *note 3 clk cmd add dq bw pixel pixel nop note 7 note 4 a x 4)block write to block write bw b t bwc *note 6
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 22/54 4. cas interrupt ( c ) : read interrupted by write & dqm (1) cl=2, bl=4 *note : 1. to prevent bus contention, there should be at least one gap between data in and data out. 2. to prevent bus contention, dqm should be issued which makes at least one gap between data in and data out. ( 2 ) cl=3 , bl=4 clk i)cmd dqm dq rd d1 d3 d0 d2 wr ii)cmd dqm dq iii)cmd dqm dq iv)cmd dqm dq d1 d3 d0 d2 rd wr rd wr d1 d3 d0 d2 d1 d3 d0 d2 rd wr hi-z q0 *note1 hi-z hi-z hi-z clk i)cmd ii)cmd iii)cmd iv)cmd dqm dqm dqm dqm dq dq dq dq rd d1 d3 d1 d0 d2 d3 d0 d2 wr rd wr rd wr d1 d3 d0 d2 d1 d3 d0 d2 rd wr hi-z d1 d0 d2 q0 *note2 v)cmd dqm dq rd wr hi-z d3
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 23/54 5. write interrupted by precharge & dqm *note : 1. to inhibit invalid write, dqm should be issued. 2. this precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt but only another bank precharge of dual banks operation. 6. precharge 1) normal write (bl = 4) 2) block write 3) read (bl=4) 7. auto precharge 1) normal write (bl = 4) 2) block write clk cmd dq(cl2) q0 q1 q2 q3 rd pre dq(cl3) q0 q1 q2 q3 *note2 1 2 clk cmd dqm dq d0 d1 d2 wr *note2 *note1 masked b y d q m pre d3 clk cmd dq d0 d1 d2 d3 wr *note3 auto precharge starts clk cmd dq pixel bw *note3 auto precharge starts t bal t bpl t rp clk cmd dq d0 d1 d2 d3 wr t rdl *note1 clk cmd dq pixel bw pre pre t bpl *note1
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 24/54 3) read (bl=4) *note : 1. t rdl : write data-in to pre command delay, t bpl : block write data-in to pre command delay. 2. number of valid output data after row precharge : 1, 2 for cas latency = 2, 3 respectively. 3. the row active command of the precharge bank can be issued after t rp from this point. the new read/write command of other activated bank can be issued from this point. at burst read/write with auto precharge, cas interrupt of the same bank is illegal. 4. for -5s/-6s/-7s/-8s, auto precharge after a normal write starts at clock(n+bl+1). 8. burst stop & precharge interrupted 1) write interrupted by precharge (bl=4) 2) write burst stop (full page only) 3) read interrupted by precharge (bl=4) 4) read burst stop (full page only) 9. mrs & smrs 1) mode register set 2) special mode register set clk cmd dq(cl2) q0 q1 q2 q3 rd dq(cl3) q0 q1 q2 q3 *note3 auto precharge starts clk cmd dqm dq d0 d1 d2 wr *note1 clk cmd dq d0 d1 d2 wr stop t rdl d3 pre t bdl clk cmd dq(cl2) dq(cl3) q0 q1 q0 q1 rd pre *note3 clk cmd dq(cl2) q0 q1 rd stop 2 dq(cl3) q0 q1 *note3 1 2 1 clk cmd pre *note4 mrs act t rp 1clk clk cmd smrs smrs act 1clk 1clk act smrs 1clk 1clk
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 25/54 *note3 *note6 *note: 1. t rdl : 1 clk ; last data in to row precharge. 2. t bdl : 1 clk ; last data in to burst stop delay. 3. number of valid output data after row precharge or burst stop : 1, 2 for cas latency = 2, 3 respectively. 4. pre : both banks precharge, if necessary. mrs can be issued only at all banks precharge state. 10. clock suspend exit & power down exit 1) clock supend (=active power down) exit 2) power down (=precharge power down) exit 11. auto refresh & self refresh 1) auto refresh 1) self refresh *note : 1. active power down : one or more banks active state. 2. precharge power down : both banks precharge state. 3. the auto refresh is the same as cbr refresh of conventional dram. no precharge commands are required after auto refresh command. during t rc from auto refresh command, any other command can not be accepted. 4. before executing auto/self refresh command, both banks must be idle state. 5. (s)mrs, bank active, auto/self refresh, power down mode entry. 6. during self refresh mode, refresh interval and refresh operation are performed internally. after self refresh entry, self refr esh mode is kept while cke is low. clk cke internal clk cmd rd t ss *note1 clk cke internal clk cmd act t ss *note2 nop clk cmd pre ar cke cmd t rp t rc *note5 *note4 clk cmd pre sr cke cmd t rp t rc *note4
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 26/54 during self refresh mode, all input s expect cke will be don?t cared, and outputs will be in hi-z state. during t rc from self refresh exit command, any other command can not be accepted. before/after self refresh mode, burst auto refresh (2k cycles) is recommended. 12. about burst type control sequential counting at mrs a3=?0?. see the burst sequence table. (bl=4, 8) bl=1, 2, 4, 8 and full page wrap around. basic mode interleave counting at mrs a3=?1?. see the burst sequence table. (bl=4, 8) bl=4, 8. at bl=1, 2 interleave counting = sequential counting pseudo- document sequential counting at mrs a3=?1?. (see to interleave counting mode) staring address lsb 3 bits a 0-2 should be ?000? or ?111?. @bl=8 - if lsb =?000? : increment counting. - if lsb =?111? : decrement counting. for example, (assume addresses exce pt lsb 3 bits are all 0, bl=8) -- @ write, lsb =?000?, accessed co lumn in order 0-1-2-3-4-5-6-7 -- @ read, lsb =?111?, accessed column in order 7-6-5-4-3-2-1-0 at bl=4, same applications are possible. as above example, at interleave counting mode, by confining starting address to some value, pseudo-decrement counting mode can be realize. see the burst sequence table carefully. pseudo- mode pseudo- binary counting at mrs a3=?0?. (see to sequential counting mode) a0-2 =?111?. (see to full page mode) using full page mode and burst stop command, binary counting mode can be realize. -- @ sequential counting, accessed column in order 3-4-5-6-7-1-2-3 (bl=8) -- @ pseudo-binary counting accessed column in order 3-4-5-6-7-8-9-10 (burst stop command) note. the next column address of 256 is 0. random mode random column access t ccd = 1 clk every cycle read/write command with random column address can realize random column access that is similar to extended data ou t (edo) operation of conventional dram. 13. about burst length control 1 at mrs a2, 1, 0 =?000?. at auto precharge, t ras should not be violated. 2 at mrs a2, 1, 0 =?001?. at auto precharge, t ras should not be violated. 4 at mrs a2, 1, 0 =?010?. 8 at mrs a2, 1, 0 =?011?. basic mode full page at mrs a2, 1, 0 =?111?. wrap around mode (infinite burst length) should be stopped by burst stop. ras interrupt or cas interrupt.
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 27/54 brsw at mrs a9 =?1? read burst =1, 2, 4, 8, full page/write burst =1 at auto precharge of write, t ras should not be violated. special mode block write 8 column block write. lsb a0-2 are ignored. burst length =1 t ras should not be violated. at auto precharge, t ras should not be violated. random mode burst stop t bdl =1, valid dq after burst stop is 1, 2 for cl=2, 3 respectively. using burst stop command, random mode it is possible only at full page burst length. ras interrupt (interrupted by precharge) before the end of burst, row precharge command of the same bank stops read/write burst with row precharge. t rdl =1 with dqm, valid dq after burst stop is 1, 2 for cl = 2, 3 respectively during read/write burst with auto precharge, ras interrupt can not be issued. interrupt mode cas interrupt before the end of burst, new read/write stops read/write burst and starts new read/write burst or block write. during read/write burst with auto precharge, cas interrupt can not be issued. 14. mask function 1) normal write i/o masking : by mask at write per bit mode, the selected bit planes keep the original data. if bit plane 0, 3, 7, 9, 19, 22, 24 and 31 keep the original value. i) step i smrs(lmr) : load mask [31-0]=?0111, 1110, 1011, 0111, 1111, 1101, 0111, 0110? ii row active with dsf ?h? : write per bit mode enable iii perform normal write i) illustration i/o (=dq) 31 24 23 16 15 8 7 0 external data-in 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dqmi dqm3=0 dqm2=0 dqm1=0 dqm0=1 mask register 0 1 1 1 1 1 1 0 1 0 1 1 0 1 1 1 1 1 1 1 1 1 0 1 0 1 1 1 0 1 1 0 before write 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 after write 0 1 1 1 1 1 1 0 1 0 1 1 0 1 1 1 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 note 1 2) block write pixel masking : by pixel data issued through dq pin, the selected pixels keep the original data. see pixel to dq mapping table. if pixel 0, 4, 9, 13, 18, 22, 27 and 31 keep the original white color. assume 8bpp white = ?0000, 0000?, red = ?1010, 0011?, green = ? 1110, 0001?, yellow = ?0000, 1111?, blue = ?1100, 0011? i) step i smrs(lcr) : load color (for 8bpp, through x32 dq color0-3 are loaded into color registers) load (color3, color2, color1, color0) = (blue, green, yellow, red) = ?1100, 0011, 1110, 0001, 0000, 1111, 1010, 0011 ? ii row active with dsf ?l? : i/o mask by write per bit mode disable iii block write with dq[31-0] = ?0111, 0111, 1011, 1011, 1101, 1101, 1110, 1110? * note : 1. dqm byte masking.
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 28/54 (continued) i) illustration i/o (=dq) 31 24 23 16 15 8 7 0 dqmi dqm3=0 dqm2=0 dqm1=0 dqm0=1 color register color3=blue color2=green color1=yellow color0=red 000 white dq24=h white dq16=h white dq8=h white dq0=l 001 white dq25=h white dq17=h white dq9=l white dq1=h 010 white dq26=h white dq18=l white dq10=h white dq2=h 011 white dq27=l white dq19=h white dq11=h white dq3=h 100 white dq28=h white dq20=h white dq12=h white dq4=l 101 white dq29=h white dq21=h white dq13=l white dq5=h 110 white dq30=h white dq22=l white dq14=h white dq6=h before block write & dq (pixel data) 111 white dq31=l white dq23=h white dq15=h white dq7=h 000 blue green yellow white 001 blue green white white 010 blue white yellow white 011 white green yellow white 100 blue green yellow white 101 blue green white white 110 blue white yellow white after block write 111 white green yellow white note 1 pixel and i/o masking : by mask at write per bit mode , the selected bit planes keep the original data. by pixel data issued through dq pin, the selected pixels keep the original data. see pixel to dq mapping table. assume 8bpp, white = ?0000, 0000?, red = ?1010, 0011?, green = ? 1110, 0001?, yellow = ?0000, 1111?, blue = ?1100, 0011? i) step i smrs(lcr) : load color (for 8bpp, through x 32 dq color0-3 are loaded into color registers) load (color3, color2, color1, colo r0, ) = (blue, green, yellow, red) =?1100, 0011, 1110, 0001, 0000, 1111, 1010, 0011? ii smrs(lmr) load mask. mask[31-0] = ?1111.1111. 1101, 1101, 0100, 0010, 0111, 0110? ? byte 3 : no i/o masking ; byte 2 : i/o masking ; byte 1 : i/o and pixel masking ; byte 0 : dqm byte masking iii row active with dsf ?h? : i/o mask by write per bit mode enable iv block write with dq [31-0] = ?0111, 0111 .1111, 1111, 0101, 0101, 1110, 1110 ?(pixel mask) *note : 1. at normal write, one column is selected among columns decorded by a2-0 (000-111). at block write, instead of ignored address a2-0, dq0-31 control each pixel.
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 29/54 i) illustration i/o (=dq) 31 24 23 16 15 6 7 0 color register blue 1 1 0 0 0 0 1 1 green 1 1 1 0 0 0 0 1 yellow 0 0 0 0 1 1 1 1 red 1 0 1 0 0 0 1 1 dqmi dqm3=0 dqm2=0 dqm1=0 dqm0=1 mask register 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 0 1 0 0 0 0 1 0 0 1 1 1 0 1 1 0 before write yellow 0 0 0 0 1 1 1 1 yellow 0 0 0 0 1 1 1 1 green 1 1 1 0 0 0 0 1 white 0 0 0 0 0 0 0 0 after write blue 1 1 0 0 0 0 1 1 blue 1 1 0 0 0 0 1 1 red 1 0 1 0 0 0 1 1 white 0 0 0 0 0 0 0 0 i/o (=dq) 31 24 23 16 15 6 7 0 dqmi dqm3=0 dqm2=0 dqm1=0 dqm0=1 color register color3=blue color2=green color1=yellow color0=red 000 yellow dq24=h yellow dq16=h green dq8=h white dq0=l 001 yellow dq25=h yellow dq17=h green dq9=l white dq1=h 010 yellow dq26=h yellow dq18=h green dq10=h white dq2=h 011 yellow dq27=l yellow dq19=h green dq11=l white dq3=h 100 yellow dq28=h yellow dq20=h green dq12=h white dq4=l 101 yellow dq29=h yellow dq21=h green dq13=l white dq5=h 110 yellow dq30=h yellow dq22=h green dq14=h white dq6=h before block write & dq (pixel data) 111 yellow dq31=l yellow dq23=h green dq15=l white dq7=h 000 blue blue red white 001 blue blue green white 010 blue blue red white 011 yellow blue green white 100 blue blue red white 101 blue blue green white 110 blue blue red white after block write 111 yellow blue green white note 2 note 1 pixel mask i/o mask pixel & i/o mask byte mask *note : 1. dqm byte masking. 2. at normal write, one column is selected among columns decorded by a2-0(000-111) at block write, instead of ignored ad dress a2-0, dq0-31 control each pixel.
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 30/54 function truth ta ble (table 1) current state cs ras cas we dsf ba (a10) addr action note hx xxx x x nop lh hhx x x nop l h h l x x x illegal 2 l h l x x ba ca illegal 2 l l h h l ba ra row active ; latch row address ; non-io mask idle l l h h h ba ra row active ; latch row address ; io mask l l h l l x pa auto refresh or self refresh 4 l l h l h ba x nop l l l h l x x auto refresh or self refresh 5 l l l h h ba x illegal l l l l l op code mode register access 5 l l l l h op code special mode register access 6 hx xxx x x nop lh hhx x x nop l h h l x x x illegal 2 l h l h l ba ca, ap begin read ; latch ca ; determine ap l h l h h x x illegal row l h l l l ba ca, ap begin write ; latch ca ; determine ap active l h l l h ba ca, ap begin write ; latch ca ; determine ap l l h h x ba ra illegal 2 l l h l l ba ra precharge l l h l h x x illegal l l l h x x x illegal l l l l l x x illegal l l l l h op code special mode register access 6 h x x x x x x nop (continue burst to end ? row active) l h h h x x x nop (continue burst to end ? row active) l h h l l x x term burst ? row active l h h l h x x illegal l h l h l ba ca, ap term burst, begin read ; latch ca ; determine ap 3 read l h l h h x x illegal l h l l l ba ca, ap term burst, begin write ; latch ca ; determine ap 3 l h l l h ba ca, ap term burst, begin write ; latch ca ; determine ap 3 l l h h x ba ra illegal 2 l l h l l ba pa term burst, precharge timing for reads 3 l l h l h x x illegal l l l x x x x illegal h x x x x x x nop (continue burst to end ? row active) l h h h x x x nop (continue burst to end ? row active) l h h l l x x term burst ? row active write l h h l h x x illegal l h l h l ba ca, ap term burst, begin read ; latch ca ; determine ap 3 l h l h h x x illegal l h l l l ba ca, ap term burst, begin write ; latch ca ; determine ap 3 l h l l h ba ca, ap term burst, begin write ; latch ca ; determine ap 3
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 31/54 function truth table (table 1, continued) current state cs ras cas we dsf ba (a10) addr action note l l h h x ba ra illegal 2 write l l h l l ba ra term burst : precharge timing for writes 3 l l h h h x x illegal l l l x x x x illegal h x x x x x x nop(continue burst to end ? precharge) l h h h x x x nop(continue burst to end ? precharge) read with l h h l x x x illegal auto l h l h x ba ca, ap illegal 2 precharge l h l l x ba ca, ap illegal 2 l l h x x ba ra, pa illegal l l l x x x x illegal 2 h x x x x x x nop(continue burst to end ? precharge) l h h h x x x nop(continue burst to end ? precharge) write with l h h l x x x illegal auto l h l h x ba ca, ap illegal 2 precharge l h l l x ba ca, ap illegal 2 l l h x x ba ra, pa illegal l l l x x x x illegal 2 hx xxx x x nop ? idle after t rp lh hhx x x nop ? idle after t rp l h h l x x x illegal precharging l h l x x ba ca, ap illegal 2 l l h h x ba ra illegal 2 ll hlx ba pa nop ? idle after t rp 2 l l l x x x x illegal 4 hx xxx x x nop ? row active after t bwc lh hhx x x nop ? row active after t bwc block l h h l x x x illegal write l h l x x ba ca, ap illegal 2 recovering l l h h x ba ra illegal 2 ll hlx ba pa term block write : precharge timing for block write 2 l l l x x x x illegal 2 hx xxx x x nop ? row active after t rcd lh hhx x x nop ? row active after t rcd row l h h l x x x illegal activating l h l x x ba ca, ap illegal 2 l l h h x ba ra illegal 2 l l h l x ba pa illegal 2 l l l x x x x illegal 2 hx xxx x x nop ? idle after t rc lh hxx x x nop ? idle after t rc refreshing l h l x x x x illegal l l h x x x x illegal l l l x x x x illegal abbreviations : ra = row address (a0~a9) ba = bank address (a10) pa = precharge all (a9) nop = no operation command ca = column address (a0~a7) ap = auto precharge (a9)
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 32/54 function truth table (table 1, continued) *note : 1. all entries assume the cke was active (high) during the preceding cl ock cycle and the current clock cycle. 2. illegal to bank in specified state ; function may be legal in the bank indicated by ba, depending on the state of that bank. 3. must satisfy bus contention, bus turn around, and/or write recovery requirements. 4. nop to bank precharging or in idle state. may precharge bank indicated by ba (and pa). 5. illegal if any bank is not idle. 6. legal only if all banks are in idle or row active state. function truth table for cke (table2) current state cke ( n-1 ) cke n cs ras cas we dsf addr action note h x x x x x x x invalid lhhxxxxx exit self refresh ? abi after t rc 7 self l h l h h h x x exit self refresh ? abi after t rc 7 refresh l h l h h l x x illegal l h l h l x x x illegal l h l l x x x x illegal l l x x x x x x nop (maintain self refresh) h x x x x x x x invalid both l h h x x x x x exit power down ? abi 8 bank l h l h h h x x exit power down ? abi 8 precharge l h l h h l x x illegal power l h l h l x x x illegal down l h l l x x x x illegal l l x x x x x x nop (maintain low power mode) h h x x x x x x refer to table 1 h l h x x x x x enter power down 9 h l l h h h x x enter power down 9 all h l l h h l x x illegal banks h l l h l x x x illegal idle h l l l h x x x illegal hllllhxx enter self refresh 9 h l l l l l x x illegal l l x x x x x x nop any state h h x x x x x x refer to operations in table 1 other than h l x x x x x x begin clock suspend next cycle 10 listed l h x x x x x x exit clock suspend next cycle 10 above l l x x x x x x maintain clock suspend abbreviations : abi = all banks idle *note : 7.after cke?s low to high transition to exit self refresh mode. and a time of t rc(min) has to be elapse after cke?s low to high transition to issue a new command. 8.cke low to high transition is asynchronous as if restart internal clock. a minimum setup time ? t ss + one clock ? must be satisfy before any command other than exit. 9.power down and self refresh can be entered only from the all banks idle state. 10.must be a legal command.
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 33/54 power on sequence & auto refresh clock cke cs ras cas addr we dsf dq a10/ba a9/ap auto refresh :don't care precharge (all banks) dqm row active (write per bit enable or disable) 2 13 45 6 7 8 910 11 12 13 14 15 16 17 18 19 high level is necessary 0 key ra bs key ra key high level is necessary high-z auto refresh mode register set t rp t rc
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 34/54 single bit read-write-read cycle (same p age) @cas latency = 3, burst length = 1 clock cke cs ras cas addr we dsf dq a10 a9 read :don't care row active (write per bit enable or disable) dqm row active (write per bit enable or disable) 2 13 45 6 7 8 910 11 12 13 14 15 16 17 18 19 0 rb write or block write read t rcd t ch t cl t cc high t ras t rc t sh t ss t rp *note1 t sh t ss t ccd t sh t ss ra ca cb cc t sh t ss t sh t ss bs bs bs bs bs bs *note2 *note2,3 *note2,3 *note2,3 *note4 *note2 rb ra *note3 *note3 *note3 *note4 t sh t ss *note6 *note5 *note5 qa db qc t sac t rac t slz t oh t ss t sh t shz t ss precharge t ss t sh t sh
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 35/54 * note : 1. all input can be don?t care when cs is high at the clk high going edge. 2. bank active & read/write are controlled by a10. a10 active & read/write 0bank a 1bank b 3. enable and disable auto precharge function are controlled by a9 in read/write command. a9 a10 operation 0 disable auto precharge, leave bank a active at end of burst. 0 1 disable auto precharge, leave bank b active at end of burst. 0 enable auto precharge, prechar ge bank a at end of burst. 1 1 enable auto precharge, prechar ge bank b at end of burst. 4. a9 and a10 control bank precharge when precharge command is asserted. a9 a10 precharge 00 bank a 01 bank b 1 x both bank 5. enable and disable write-per bit function are controlled by dsf in row active command. a10 dsf operation l bank a row active, disable write per bit function for bank a. 0 h bank a row active, enable write per bit function for bank a. l bank b row active, disable write per bit function for bank b. 1 h bank b row active, enable write per bit function for bank b. 6. block write/normal write is controlled by dsf. dsf operation minimum cycle time l normal write t ccd h block write t bwc
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 36/54 read & write cycle at same bank @ burst length = 4 *note : 1. minimum row cycle time is requi red to complete internal dram operation. 2. row precharge can interrupt burst on any cycle.[cas length - 1] valid output data av ailable after row. enters precharge. la st valid output will be hi-z after t shz from the clock. 3. access time from row address. t cc *( t rcd +cas latency - 1) + t sac 4. output will be hi-z after the end of burst. (1, 2, 4 & 8) at full page bit burst, burst is wrap-around. clock cke cs ras cas addr we dsf dq cl=2 a10 a9 read (a-bank) :don't care row active (a-bank) dqm 2 13 45 6 7 8 910 11 12 13 14 15 16 17 18 19 0 cb0 precharge (a-bank) row active (a-bank) t rcd high t rc *note1 ra ca0 rb rb ra qa1 qa3 db0 t oh t rac t sac t shz qa0 qa2 *note3 *note2 *note4 db1 db3 db2 t rdl cl = 3 qa1 db1 qa3 db3 db0 db2 t oh t rac t sac t shz t rdl qa0 qa2 *note3 *note4 write (a-bank) precharge (a-bank)
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 37/54 page read & write cycle sa me bank @ burst length = 4 * note : 1.to write data before burst read ends, dqm should be asserted three cycle prior to write command to avoid bus contention. 2. row precharge will interrupt writing. last data input, t rdl before row precharge, will be written. 3. dqm should mask invalid input data on precharge command cycle when asserting precharge before end of burst. input data after row precharge cycle will be masked internally. clock cke cs ras cas addr we dsf dq cl=2 a10 a9 read (a-bank) :don't care row active (a-bank) dqm 2 13 45 6 7 8 910 11 12 13 14 15 16 17 18 19 0 cd0 t rcd high ra ca0 cc0 ra qa1 qb1 dc0 qa0 qb0 dc1 dd0 cl = 3 qa1 dc1 dd1 dc0 dd0 qa0 qb0 write (a-bank) precharge (a-bank) cb0 t rdl t cdl *note2 *note2 *note1 *note3 dd1 read (a-bank) write (a-bank)
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 38/54 block write cycle (with auto precharge) *note : 1. column mask (dqi = l : mask, dqi = h : non mask) 2. t bwc : block write cycle time 3. at block write, second cycle should be in nop. other bank can be active or precharge. 4. at block write. ca0-2 are ignored. clock cke cs ras cas addr we dsf dq a10 a9 masked block w rite (a-bank) :don't care row active with write-per-bit enable (a-bank) dqm 2 134 56 78 9 10 11 12 13 14 15 16 17 18 19 0 cba high raa caa rba raa pixel mask block write (b-bank) block write with auto precharge (b-bank) cab *note2 *note1 *note3 row active (b-bank) *note4 cbb rba t bwc pixel mask pixel mask pixel mask masked block write with auto precharge (a-bank)
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 39/54 smrs and block/normal write @ burst length = 4 *note : 1. at the next clock of special mode register set command, new command is possible. clock cke cs ras cas a0-2 we dsf dq a3,4,7,8 a5 load mask register :don't care load color register dqm 2 134 56 78 9 10 11 12 13 14 15 16 17 18 19 0 high masked write with auto precharge (b-bank) load color register *note1 masked block write (a-bank) raa rba caa cba raa rba cba caa cba raa rba a6 caa cba raa rba a9 raa rba a9 pixel mask color i/o mask dba0 dba1 dba2 dba3 color i/o mask row active with wpb* enable (a-bank) row active with wpb* enable (b-bank) load mask register wpb* : write-per-bit
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 40/54 page read cycle at differe nt bank @ burst length = 4 *note : 1. cs can be don?t care when ras , cas and we are high at the clock high going edge. 2. to interrupt a burst read by row precharge, both the read and the precharge banks must be the same. clock cke cs ras cas addr we dsf dq cl=2 a10 a9 read (a-bank) :don't care row active (a-bank) dqm 2 13 45 6 7 8 910 11 12 13 14 15 16 17 18 19 0 cbd precharge (a-bank) high raa caa cac raa qaa1 qaa3 qbb1 qaa0 qaa2 qbb2 qbb3 cl = 3 read (b-bank) read (a-bank) rbb *note1` qac0 row active (b-bank) read (a-bank) rbb *note2` cbb cae low qbb0 qac1 qbd0 qbd1 qae0 qae1 qaa1 qaa3 qbb1 qaa0 qaa2 qbb2 qbb3 qac0 qbb0 qac1 qbd0 qbd1 qae0 qae1 read (b-bank)
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 41/54 page write cycle at diffe rent bank @ burst length =4 clock cke cs ras cas addr we dsf a10 a9 masked write (a-bank) :don't care row active with write-per-bit enable (a-bank) dqm 2 13 45 6 7 8 910 11 12 13 14 15 16 17 18 19 0 high raa caa cac raa daa1 daa3 dbb1 daa0 daa2 dbb2 dbb3 dq rbb dac0 row active (b-bank) masked write with auto precharge (a-bank) rbb cbb cbd dbb0 dac1 dac3 dbd0 dbd1 write (b-bank) write with auto precharge (b-bank) key t cdl mask dac2 dbd2 dbd3 load mask register
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 42/54 read & write cycle at diffe rent bank @ burst length =4 *note : 1. t cdl should be met to complete write. clock cke cs ras cas addr we dsf a10 a9 :don't care row active (a-bank) dqm 2 13 45 6 7 8 910 11 12 13 14 15 16 17 18 19 0 high raa caa cbb raa qaa1 qaa3 qaa0 dq cl=2 dbb0 row active (b-bank) rbb cac qaa2 dbb1 dbb3 qac0 precharge (a-bank) read (a-bank) t cdl dbb2 qac1 qac2 rac rbb rac qaa1 qaa3 qaa0 cl=3 dbb0 qaa2 dbb1 dbb3 qac0 dbb2 qac1 read (a-bank) write (b-bank) row active (a-bank) *note1
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 43/54 read & write cycle with auto precharge @ burst length =4 *note : 1. t rdl should be controlled to meet minimum t ras before internal precharge start. (in the case of burst length = 1 & 2, brsw mode and block write) clock cke cs ras cas addr we dsf a10 a9 :don't care row active (a-bank) dqm 2 13 45 6 7 8 910 11 12 13 14 15 16 17 18 19 0 high ra rb ra qa1 qa3 qa0 dq cl=2 db0 ca qa2 db1 db3 auot precharge start point (a-bank) db2 cb cl=3 row active (b-bank) write with auto precharge (b-bank) rb qa1 qa3 qa0 db0 qa2 db1 db3 db2 read with auto precharge (a-bank) auot precharge start point (b-bank)
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 44/54 read & write cycle with auto precharge ii @ burst length =4 *note : 1. when read(write) command with auto precharge is issued at a-bank after a and b bank activation. - if read(write) command without auto precharge is issued at b-bank before a bank auto precharge starts, a bank auto precharge will start at the next cy cle of b bank read command input point. - any command can not be issued at a bank during t rp after a bank auto precharge starts. clock cke cs ras cas addr we dsf a10 a9 :don't care row active (a-bank) dqm 2 13 45 6 7 8 910 11 12 13 14 15 16 17 18 19 0 high ra rb ra qa1 qb1 qa0 dq cl=2 db2 ca qb0 db3 da1 read without auto precharge(b-bank) da0 row active (b-bank) precharge (b-bank) rb read with auto precharge (a-bank) write with auot precharge (a-bank) cb ra ca ra qa1 qb1 qa0 db2 qb0 db3 da1 da0 row active (a-bank) autopreaharge start point (a-bank)
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 45/54 read & write cycle with auto precharge iii @ burst length =4 *note : 1. any command to a bank is not allowed in this period. t rp is determined from at auto precharge start point. clock cke cs ras cas addr we dsf a10 a9 :don't care row active (a-bank) dqm 2 13 45 6 7 8 910 11 12 13 14 15 16 17 18 19 0 high ra rb ra qa1 qa3 qa0 dq cl=2 db0 ca qa2 db1 db3 auot precharge start point (a-bank) row active (b-bank) db2 cb cl=3 rb qa1 qa3 qa0 db0 qa2 db1 db3 db2 read with auto precharge (a-bank) auot precharge start point (b-bank) read with auto precharge (b-bank) *note 1 t rcd
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 46/54 read interrupted by precharge command & re ad burst stop cycle (@ full page only) *note : 1. at full page mode, burst is warp-around at the end of burst. so auto precharge is impossible. 2. about the valid dq?s after burst stop, it is same as the case of ras interrupt. both cases are illustrated above timing diagram. see the label 1, 2 on them. but at burst write, burst stop and ras interrupt should be compared carefully. refer the timing diagram of ?full page write burst stop cycle?. 3. burst stop is valid at full page mode. clock cke cs ras cas addr we dsf a10 a9 :don't care row active (a-bank) dqm 2 13 45 6 7 8 910 11 12 13 14 15 16 17 18 19 0 high raa raa qaa1 qaa3 qaa0 dq cl=2 dab0 caa qaa2 dab1 dab3 burst stop dab2 cab cl=3 read (a-bank) precharge (a-bank) read (a-bank) *note 1 *note 1 qaa4 dab5 dab4 1 1 *note 2 qaa1 qaa3 qaa0 dab0 qaa2 dab1 dab3 dab2 qaa4 dab5 dab4 2 2
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 47/54 write interrupted by precharge command & wr ite burst stop cycle (@ full page only) *note : 1. at full page mode, burst is warp-around at the end of burst. so auto precharge is impossible. 2. data-in at the cycle of burst stop command cannot be written into the corresponding memory cell. it is defined by ac parameter of t bdl (=1clk). 3. data-in at the cycle interrupted by precharge cannot be written into the corresponding memory cell. it is defined by ac parameter of t rdl (=1clk). dqm at write interrupted by precharge command is needed to ensure t rdl of 1clk. dqm should mask invalid input data on precharge command cycle when asserting precharge before end of burst. input data after row precharge cycle will be masked internally. 4. burst stop is valid only at full page burst length. clock cke cs ras cas addr we dsf dq a10 a9 write (a-bank) write (a-bank) :don't care row active (a-bank) dqm 2 134 56 78 9 10 11 12 13 14 15 16 17 18 19 0 cab high raa caa raa precharge (a-bank) *note3 burst stop *note1 *note1 t bdl t rdl *note2 daa3 daa4 daa0 daa1 daa2 dab3 dab4 dab0 dab1 dab2 dab5
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 48/54 burst read single bit write cycle @ burst length = 2, brsw *note : 1. brsw mode is enabled by setting a9 ?high? at mrs (mode register set). at the brsw mode, the burst length at write is fixed to ?1? regardless of programed burst length. 2. when brsw write command with auto precharge is executed, keep it in mind that t ras should not be violated. auto precharge is executed at the burst-end cycle, so in the case of brsw write command. the next cycle is also starts the precharge. 3. wpb function is also possible at brsw mode. clock cke cs ras cas addr we dsf a10 a9 :don't care row active (a-bank) dqm 2 13 45 6 7 8 910 11 12 13 14 15 16 17 18 19 0 high raa raa qaa0 dab0 caa dab1 dad0 row active (b-bank) dbc0 rab cl=3 write (a-bank) precharge (a-bank) row active (a-bank) *note 1 dad1 *note 2 cab rbb cbc cad rbb rac read with auto precharge (a-bank) write with auto precharge (b-bank) read (a-bank) qaa0 dab0 dab1 dad0 dbc0 dad1
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 49/54 clock suspension & dqm operation cycl e @ cas latency = 2, burst length = 4 *note : 1. dqm needed to prevent bus contention. clock cke cs ras cas addr we dsf a10 a9 :don't care row active dqm 2 13 45 6 7 8 910 11 12 13 14 15 16 17 18 19 0 ra ra qa0 dq qa1 ca qa3 dc0 clock suspension cb write write dqm read clock suspension read cc read dqm qa2 qb0 qb1 t shz t shz dc2 *note1
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 50/54 active/precharge power down mode @ cas latency = 2, burst length =4 *note : 1. all banks should be in idle state prior to entering precharge power down mode. 2. cke should be set high at lease ?1clk + t ss ? prior to row active command. 3. cannot violate minimum refresh specification. (32ms) clock cke cs ras cas addr we dsf a10 a9 :don't care precharge power-down entry dqm 2 13 45 6 7 8 910 11 12 13 14 15 16 17 18 19 0 ra ra qa0 dq qa1 ca qa2 read precharge t ss t ss *note 2 *note 1 *note 3 t ss t ss precharge power-down exit row active active power-down entry active power-down exit
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 51/54 self refresh entry & exit cycle *note : to enter self refresh mode 1. cs , ras & cas with cke should be low at the same clock cycle. 2. after 1 clock cycle, all the inputs including th e system clock can be don?t care except for cke. 3. the device remains in self refresh mode as long as cke stays ?low?. cf.) once the device enters self refresh mode minimum t ras is required before exit from self refresh. to exit self refresh mode 4. system clock restart and be stable before returning cke high. 5. cs starts from high. 6. minimum t rc is required after cke going high to complete self refresh exit. 7. 2k cycle of burst auto refresh is required befo re self refresh entry an d after self refresh exit if the system uses burst refresh. clock cke cs ras cas addr we dsf a10 a9 :don't care self refresh entry dqm 2 13 45 6 7 8 910 11 12 13 14 15 16 17 18 19 0 dq self refresh exit auto refresh t ss *note 2 *note 1 t ss *note 3 *note 4 t rc min *note 6 hi-z hi-z *note 7 *note 5 *note 7
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 52/54 mode register set cycle auto refresh cycle *both bank precharge should be completed mode register set cycle and auto refresh cycle. mode register set cycle *note : 1. cs , ras , cas & we activation and dsf of low at the same cloc k cycle with address key will set internal mode register. 2. minimum 1 clock cycles should be met before new ras activation. 3. please refer to mode register set table. clock cke cs ras cas addr we dsf :don't care mrs dqm 2 13 45 6 0 2 13 45 6 0 high key new command new command auto refresh ra 7 89 10 high *note 2 *note 1 t rc *note 3 dq hi-z hi-z
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 53/54 packing dimensions 100-lead qfp(14 x 20 mm) symbol dimension in mm dimension in inch min norm max min norm max a 3.400 0.134 a1 0.250 0.010 a2 2.650 2.970 0.104 0.117 b 0.220 0.380 0.0087 0.015 c 0.110 0.230 0.0043 0.009 d 23.000 23.200 23.400 0.906 0.913 0.921 d1 19.900 20.000 20.100 0.783 0.787 0.791 e 17.000 17.200 17.400 0.669 0.677 0.685 e1 13.900 14.000 14.100 0.547 0.551 0.555 l 0.650 0.800 0.950 0.026 0.031 0.037 l1 1.600 ref 0.063 ref e 0.650 ref 0.026 ref ? 0 7 0 7 y 0.080 0.003 l l1 detail "a" d d1 pin 1 e e1 c b e a a1 a2 seating plane 1 30 31 50 51 80 81 100
esmt M32L1632512A elite semiconductor memory technology inc. publication date : jun. 2001 revision : 1.6 54/54 important notice all rights reserved. no part of this document may be reproduced or duplicated in any form or by any means without the prior permission of esmt. the contents contained in this document ar e believed to be accu rate at the time of publication. esmt assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. the information contained herein is presen ted only as a guide or examples for the application of our products. no res ponsibility is assumed by esmt for any infringement of patents, c opyrights, or other intellectual property rights of third parties which may result from its use. no license, either express , implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of esmt or others. any semiconductor devices ma y have inherently a cert ain rate of failure. to minimize risks associated with custom er's application, adequate design and operating safeguards against injury, dama ge, or loss from such failure, should be provided by the customer when making application designs. esmt's products are not authorized for use in critical applications such as, but not limited to, life support devices or system , where failure or abnormal operation may directly affect human lives or cause phys ical injury or property damage. if products described here are to be used for such kinds of a pplication, purchaser must do its own quality assurance testing appr opriate to such applications.

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